| CPC G06F 9/384 (2013.01) [G06F 9/30181 (2013.01); G06F 9/3838 (2013.01)] | 10 Claims |
|
1. Apparatus comprising:
processing circuitry to perform data processing operations in response to instructions;
physical registers to hold data values upon which the data processing operations are performed; and
register renaming circuitry to perform register renaming to map architectural registers specified in the instructions to the physical registers in support of out-of-order execution of the instructions by the processing circuitry, wherein performing the register renaming comprises creating entries in a mapping table, the entries indicative of mappings between the architectural registers specified in the instructions and the physical registers, wherein:
the register renaming circuitry is arranged to specify operations to be performed by the processing circuitry with respect to the physical registers in dependence on the instructions and on the entries in the mapping table,
when for a first instruction an entry in the mapping table is indicative of a mapping to a first instruction destination physical register for a first instruction destination architectural register specified in the first instruction,
the register renaming circuitry is responsive to a second instruction which specifies the first instruction destination architectural register as a second instruction source architectural register to adapt a specification of a second operation to generate an adapted second operation to be performed by the processing circuitry corresponding to the second instruction to use at least one first instruction source physical register as at least one second instruction source physical register, and wherein the adapted second operation incorporates a first operation corresponding to the first instruction,
the register renaming circuitry is further responsive to the first instruction to create a supplementary entry in the mapping table,
the supplementary entry is indicative of a mapping of the first instruction destination architectural register to the at least one first instruction source physical register and is indicative of a type of the first instruction,
the at least one first instruction source physical register is mapped in the mapping table to at least one first instruction source architectural register specified in the first instruction,
the register renaming circuitry is further responsive to the second instruction which specifies the first instruction destination architectural register as the second instruction source architectural register, when the supplementary entry is present in the mapping table, to adapt the specification of the second operation with reference to the supplementary entry,
the second instruction specifies a second instruction destination architectural register, and
in response to a third instruction specifying a fusible operation and specifying the second instruction destination architectural register as a third instruction source architectural register, the register renaming circuitry is configured to avoid adaptation of a third operation corresponding to the third instruction to incorporate the second operation as adapted to incorporate the first operation corresponding to the first instruction.
|