US 12,405,798 B2
Instruction processing apparatus and instruction processing method
Masahiro Goshima, Chiyoda (JP); and Yi Ge, Bunkyo (JP)
Assigned to Fujitsu Limited, Kawasaki (JP); and Inter-University Research Institute Corporation Research Organization of Information and Systems, Tokyo (JP)
Filed by Fujitsu Limited, Kawasaki (JP); and Inter-University Research Institute Corporation Research Organization of Information and Systems, Tachikawa (JP)
Filed on Jun. 13, 2023, as Appl. No. 18/209,317.
Claims priority of application No. 2022-128821 (JP), filed on Aug. 12, 2022.
Prior Publication US 2024/0053990 A1, Feb. 15, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3836 (2013.01) [G06F 9/30145 (2013.01); G06F 9/3826 (2013.01); G06F 9/3838 (2013.01); G06F 9/3858 (2023.08); G06F 9/3001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An instruction processing apparatus comprising a processor configured to execute a process including:
issuing, by an instruction scheduler, instructions that can be executed;
holding, by a register file, data used by the instructions;
executing, by an execution unit including a plurality of stages, the instructions issued by the instruction scheduler;
detecting, by a detector, early termination in which an execution result of an intermediate stage, which is before a final stage among the plurality of stages, is the same as an execution result of the execution unit; and
transferring, by a bypass controller, the data from the register file or the execution result from the execution unit, to an input of the execution unit, and in response to the detector detecting the early termination, bypassing the execution result of the intermediate stage to the input of the execution unit.