US 12,405,794 B2
Signal processing apparatus and non-transitory computer-readable storage medium
Takeshi Ogawa, Tokyo (JP)
Assigned to CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Jun. 6, 2023, as Appl. No. 18/329,738.
Claims priority of application No. 2022-099799 (JP), filed on Jun. 21, 2022.
Prior Publication US 2023/0409323 A1, Dec. 21, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01)
CPC G06F 9/30134 (2013.01) [G06F 9/30098 (2013.01); G06F 9/30105 (2013.01); G06F 9/3012 (2013.01); G06F 9/3885 (2013.01); G06F 15/8076 (2013.01); G06F 15/8092 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A signal processing apparatus comprising:
a central processing unit (CPU); and
a programmable signal processing circuit having the following:
a plurality of execution circuits each of which has a program memory and executes a program stored in the program memory,
wherein the plurality of execution circuits can operate in parallel;
a register file used for the plurality of execution circuits,
wherein the register file has a plurality of registers serially connected and transfers, in accordance with a shift signal, data held by each of the plurality of registers to a register located downstream;
a shift controller that issues the shift signal to the plurality of execution circuits at a timing at which the plurality of execution circuits do not execute the program,
wherein the CPU stores, to each program memory of the plurality of execution circuits, a program including instructions to make a register of the register file located upstream of a register that a second execution circuit of the plurality of execution circuits is to reference in order to input data be a storage destination for data of a result by execution of the program by a first execution circuit of the plurality of execution circuits so that the data of the result by the execution of the program by the first execution circuit is transferred to the second execution circuit via the register file.