US 12,405,792 B2
Processing unit including a dynamically allocatable vector register file for non-vector instruction processing
Hithesh Hassan Lepaksha, Hyderabad (IN); Darshan Kumar Nandanwar, Bangalore (IN); and Sagar Bamashetti, Chadchan (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 27, 2023, as Appl. No. 18/475,320.
Prior Publication US 2025/0103335 A1, Mar. 27, 2025
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/3013 (2013.01) [G06F 9/30036 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processing unit comprising:
one or more non-vector processing circuits;
a vector register file comprising:
a first portion designated for vector registers; and
a queue buffer configured to receive a plurality of vector instructions;
the processing unit configured to:
determine a vector register requirement for execution of the plurality of vector instructions;
in response to determining that the vector register requirement for execution of the plurality of vector instructions is less than substantially all of the first portion designated for the vector registers, allocate a first subset of the first portion designated for the vector registers to the one or more non-vector processing circuits leaving a complement portion of the first portion designated for the vector registers;
execute the plurality of vector instructions; and
in response to determining that that the vector register requirement for execution of the plurality of vector instructions is more than the complement portion of the first portion designated for the vector registers, reallocate a second portion of the first subset to the vector registers,
wherein the one or more non-vector processing circuits comprises:
a miss buffer circuit;
a load/store buffer circuit; and
an integer instruction scheduler circuit, and
wherein the processing unit configured to reallocate the second portion of the first subset to the vector registers is further configured to:
reallocate the second portion of the first subset which was allocated to the miss buffer circuit.