US 12,405,790 B2
Compute unit sorting for reduced divergence
David Ronald Oldcorn, Milton Keynes (GB); and Skyler Jonathon Saleh, La Jolla, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 28, 2019, as Appl. No. 16/457,873.
Prior Publication US 2020/0409695 A1, Dec. 31, 2020
Int. Cl. G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/38 (2018.01); G06F 8/41 (2018.01)
CPC G06F 9/3005 (2013.01) [G06F 9/30058 (2013.01); G06F 9/323 (2023.08); G06F 9/3851 (2013.01); G06F 9/3887 (2013.01); G06F 9/38873 (2023.08); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08); G06F 8/41 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for reducing divergence of control flow in a single-instruction-multiple-data processor, the method comprising:
at a point of divergent control flow, identifying control flow targets for different execution items of a wavefront having a plurality of time slots;
sorting the execution items based on the identified control flow targets, to generate sorted execution item groups;
reorganizing the execution items of the wavefront across the time slots based on the sorted execution item groups such that within a time slot of the time slots more execution items have the same control flow target than without the reorganizing; and
executing the wavefront after the point of divergent control flow.