US 12,405,789 B2
Load chunk instruction and store chunk instruction
Alasdair Grant, Cambridge (GB); and Stuart Robert Douglas Monteith, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 18/260,972
Filed by Arm Limited, Cambridge (GB)
PCT Filed Dec. 9, 2021, PCT No. PCT/GB2021/053218
§ 371(c)(1), (2) Date Jul. 11, 2023,
PCT Pub. No. WO2022/153024, PCT Pub. Date Jul. 21, 2022.
Claims priority of application No. 2100503 (GB), filed on Jan. 15, 2021.
Prior Publication US 2024/0061682 A1, Feb. 22, 2024
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30043 (2013.01) [G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/30181 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an instruction decoder to decode instructions; and
processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder; in which:
in response to the instruction decoder decoding a load chunk instruction specifying a source address, at least one architecturally visible load destination register, and an architecturally visible load length register, the processing circuitry is configured to:
determine, based on at least one implementation-specific condition, a first number of bytes indicative of how many bytes of data to load from a memory system in response to the load chunk instruction;
load data from a source block of memory system locations selected based on the source address and designate at least a portion of the loaded data as data corresponding to the at least one architecturally visible load destination register, the source block of memory system locations having a size corresponding to the first number of bytes; and
designate a load length value as data corresponding to the architecturally visible load length register, the load length value indicative of a number of bytes which is less than or equal to the first number of bytes and which is also less than or equal to a number of bytes corresponding to a total size of the at least one architecturally visible load destination register; and
in response to the instruction decoder decoding a store chunk instruction specifying a destination address, at least one architecturally visible store source register, and an architecturally visible store length register, the processing circuitry is configured to:
determine, based on at least one implementation-specific condition, a second number of bytes indicative of how many bytes of data to store to the memory system in response to the store chunk instruction;
store data, at least a portion of which is data designated as corresponding to the at least one architecturally visible store source register, to a destination block of memory system locations determined based on the destination address, the destination block of memory system locations having a size corresponding to the second number of bytes; and
designate a store length value indicative of the second number of bytes as data corresponding to the architecturally visible store length register.