US 12,405,786 B1
Hardware support for conversion between integer and floating-point data
Christopher A. Burns, Austin, TX (US); Terence M. Potter, Austin, TX (US); and Yoong Chert Foo, London (GB)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 27, 2024, as Appl. No. 18/588,724.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30014 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
floating-point pipeline circuitry configured to execute a single instruction to convert an N-bit integer value to an M-bit floating-point result, the floating-point pipeline circuitry comprising:
source modifier circuitry configured to generate an intermediate M-bit representation based on the N-bit integer value; and
fused multiply-add circuitry configured to perform a fused multiply-add operation to generate the M-bit floating-point result, wherein the fused multiply-add operation operates on:
the intermediate M-bit representation;
a quantization scale factor value indicated by the instruction; and
a zero-point value indicated by the instruction.