| CPC G06F 3/0664 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] | 18 Claims |

|
1. A processor-based device, comprising a virtualization circuit communicatively coupled to a byte-addressable storage device and a block-addressable storage device;
the virtualization circuit configured to:
present, to a processor of the processor-based device, the byte-addressable storage device and the block-addressable storage device as a single virtual storage device;
generate a usage statistic for each of the byte-addressable storage device and the block-addressable storage device;
identify a low-activity region in the byte-addressable storage device based on the usage statistic for the byte-addressable storage device;
identify a high-activity region in the block-addressable storage device based on the usage statistic for the block-addressable storage device; and
exchange a first storage region corresponding to the low-activity region and comprising a memory address region of the byte-addressable storage device with a second storage region corresponding to the high-activity region and comprising a block region of the block-addressable storage device;
wherein:
the single virtual storage device is configurably presented as one of a byte-addressable virtual storage device and a block-addressable virtual storage device;
the high-activity region comprises a block-addressable storage region for which the corresponding usage statistic exceeds a value of a promotion threshold; and
the low-activity region comprises a byte-addressable storage region for which the corresponding usage statistic is lower than the usage statistic for the high-activity region.
|