| CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] | 10 Claims |
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1. A buffer chip comprising:
a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller;
a chip ID reception circuit for receiving chip ID information transmitted from the memory controller;
a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information; and
a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips;
a command address reception circuit for receiving command address signals transmitted from the memory controller;
a command address delay circuit that delays, by a set latency, the command address signals received by the command address reception circuit;
a command address transmission circuit for transmitting the command address signals delayed by the command address delay circuit to the plurality of memory chips; and
a setting change circuit for changing a command address latency of the plurality of memory chips to be different from a setting value of the memory controller.
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