CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0635 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 12/0815 (2013.01)] | 19 Claims |
1. An apparatus comprising:
at least one processing device comprising a processor coupled to a memory;
wherein the at least one processing device is configured:
to store a mapping for each of a plurality of logical storage devices of a storage system, the mapping for a given one of the logical storage devices assigning different ranges of logical block addresses of the given logical storage device to respective different cache entities of the storage system;
to receive at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device;
to modify the stored mapping for the given logical storage device based at least in part on the at least one received mapping-related communication; and
to send at least one mapping-related communication to at least one of the first and second host devices based at least in part on the modified stored mapping;
wherein receiving at least one mapping-related communication from at least one of first and second host devices that have shared access to the given logical storage device comprises receiving a notification from the first host device indicating that the first host device has generated a new mapping entry;
wherein modifying of the stored mapping for the given logical storage device is controlled based at least in part on results of performance of a consistency check between the new mapping entry and one or more existing mapping entries of the stored mapping; and
wherein the stored mapping is modified to include the new mapping entry responsive to a determination that there is no inconsistency between the new mapping entry and any corresponding existing mapping entry of the stored mapping.
|