US 12,405,726 B2
Managing write command execution during a power failure in a memory sub-system
Raja V.S. Halaharivi, Gilroy, CA (US); and Yoav Weinberg, Toronto (CA)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 15, 2024, as Appl. No. 18/606,794.
Claims priority of provisional application 63/492,042, filed on Mar. 24, 2023.
Prior Publication US 2024/0319873 A1, Sep. 26, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0608 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
detecting an asynchronous power loss event at the memory device;
receiving, from a host system, a memory access command;
determining that a size of the memory access command satisfies a threshold criterion, wherein the threshold criterion corresponds to an atomic write unit size;
responsive to determining that the size of the memory access command satisfies the threshold criterion, allocating one or more resources for executing the memory access command;
executing the memory access command using a hardware component of the memory device; and
responsive to executing the memory access command, notifying the host system of completion of execution of the memory access command.