US 12,405,651 B2
Autonomously managing core cluster frequencies using performance statistics in processor devices
Mahadevamurty Nemani, San Diego, CA (US); Anubhav Mishra, Fremont, CA (US); Arun Sukheja, San Diego, CA (US); Nitin Makhija, San Jose, CA (US); and Adarsh Baraka Ravi, San Jose, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 15, 2023, as Appl. No. 18/468,242.
Prior Publication US 2025/0093931 A1, Mar. 20, 2025
Int. Cl. G06F 1/00 (2006.01); G06F 1/28 (2006.01); G06F 9/445 (2018.01)
CPC G06F 1/28 (2013.01) [G06F 9/44505 (2013.01)] 34 Claims
OG exemplary drawing
 
1. A processor device comprising:
a core cluster comprising:
a plurality of processor cores comprising a corresponding plurality of Activity Management Units (AMUs);
a cluster power management circuit; and
a dynamic voltage and frequency scaling (DVFS) circuit; and
the cluster power management circuit configured to:
collect a plurality of AMU statistics from the plurality of AMUs for each frequency operating point of one or more frequency operating points over a time interval;
generate, based on the plurality of AMU statistics, a performance model representing processor performance as a function of frequency;
generate, based on the performance model and a power consumption measurement, an energy-per-instruction (EI) model representing energy per instruction as a function of frequency;
generate an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency;
identify a target frequency operating point based on the advantage model; and
transmit the target frequency operating point to the DVFS circuit,
wherein the DVFS circuit is configured to:
receive the target frequency operating point from the cluster power management circuit; and
set a frequency of the core cluster based on the target frequency operating point.