| CPC G06F 1/06 (2013.01) [H03K 3/037 (2013.01); H03K 5/00006 (2013.01); H03K 5/13 (2013.01); H03K 5/1534 (2013.01); H03K 2005/00058 (2013.01)] | 20 Claims |
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1. An integrated circuit comprising:
a plurality of chained clock dividers configured to receive a root clock and configured to provide a plurality of generated clocks generated from the root clock, each clock divider of the plurality of chained clock dividers provides a generated clock of the plurality of generated clocks having a lower frequency that its corresponding input clock and which transitions at falling edges of its corresponding input clock;
clock gating circuitry configured to receive the plurality of generated clocks and selectively gate the plurality of generated clocks based on a clock ready signal, wherein the clock gating circuitry is configured to provide the plurality of generated clocks as a corresponding plurality of safe clocks when the clock ready indicator indicates the plurality of generated clocks are ready;
a delay circuit having an inverted clock input configured to receive a final generated clock from the plurality of generated clocks and configured to provide a trigger output in response to a falling edge of the final generated clock; and
a set of synchronization flip flops configured to receive a clock enable signal and the trigger output from the delay circuit, and configured to provide the clock ready indicator based on the clock enable signal and the trigger output,
wherein the delay circuit asserts the trigger output by providing a rising edge at a delay time after the falling edge of the final generated clock, and the delay time is determined based on satisfying one or more conditions selected from a group of conditions consisting of a count of falling edges of the final generated clock, an estimated amplitude of a core clock, an estimated duty cycle of the root clock, a frequency of a selected clock.
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