US 12,405,622 B2
Voltage detector in data communication interface
Bengt Stefan Gustavsson, Rancho Santa Fe, CA (US); Louis Dominic Oliveira, San Diego, CA (US); Tomer Saraf, Jamaica Plain, MA (US); Robert John Littrell, Belmont, MA (US); Ganesh Kiran, San Diego, CA (US); and William Wei-Ting Kuo, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Oct. 31, 2023, as Appl. No. 18/498,927.
Claims priority of provisional application 63/514,071, filed on Jul. 17, 2023.
Prior Publication US 2025/0028341 A1, Jan. 23, 2025
Int. Cl. G05F 1/56 (2006.01); G06F 1/10 (2006.01); H03K 5/125 (2006.01); H03K 5/24 (2006.01)
CPC G05F 1/56 (2013.01) [G06F 1/10 (2013.01); H03K 5/125 (2013.01); H03K 5/24 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a clock line voltage detector configured to detect a voltage level of a clock signal sent by a host device on a clock line of a data communication interface between the apparatus and the host device, wherein the voltage level comprises a first voltage level or a second voltage level, wherein the first voltage level is higher than the second voltage level, wherein the clock line voltage detector comprises:
a comparator configured to compare a clock line voltage of the clock signal with a threshold voltage to produce a comparator output indicative of the detected voltage level; and
a low pass filter configured to filter the clock signal and to provide a filtered clock signal to the comparator, wherein a cutoff frequency of the low pass filter is set to a multiple of the first voltage level to prevent false detection of the first voltage level by the comparator; and
a circuit configured to provide an output voltage on the data communication interface, the output voltage being one of the first voltage level or the second voltage level corresponding to the detected voltage level.