US 12,405,526 B2
Extreme ultraviolet lithography patterning with assist features
Leonard Guler, Hillsboro, OR (US); Tahir Ghani, Portland, OR (US); Charles Wallace, Portland, OR (US); Hossam Abdallah, Portland, OR (US); Dario Farias, Portland, OR (US); Tsuan-Chung Chang, Portland, OR (US); Chia-Ho Tsai, Hillsboro, OR (US); Chetana Singh, Portland, OR (US); Desalegne Teweldebrhan, Sherwood, OR (US); Robert Joachim, Beaverton, OR (US); and Shengsi Liu, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,446.
Prior Publication US 2022/0413376 A1, Dec. 29, 2022
Int. Cl. G03F 1/22 (2012.01); G03F 7/20 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01)
CPC G03F 1/22 (2013.01) [G03F 7/2004 (2013.01); G03F 7/2026 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit, comprising:
patterning a plurality of semiconductor fins and one or more assist features in a substrate using extreme ultraviolet (EUV) lithography;
embedding the semiconductor fins and the one or more assist features in a fill material;
forming a mask over the fill material, wherein the mask covers a first portion of the fill material over a first semiconductor fin and exposes a second portion of the fill material over a first assist feature, the first assist feature substantially parallel to and immediately adjacent the first semiconductor fin, wherein the first semiconductor fin has a lateral width of not more than 10 nm and the first assist feature has a lateral width of not less than 100 nm;
removing at least a portion of the first assist feature, wherein the first semiconductor fin is over a first region of the substrate and the first assist feature is over a second region of the substrate, wherein removing at least the portion of the first assist feature removes an entirety of a top portion of the first assist feature, leaving a second portion of the first assist feature extending above an adjacent region of the substrate, wherein the second portion of the first assist feature comprises a first ridge, a second ridge, and a surface between the first ridge and the second ridge, wherein the surface is above the adjacent region of the substrate, and wherein the first ridge and the second ridge are each above the surface; and
forming a gate coupled to the first semiconductor fin, wherein at least a portion of the gate is over at least a portion of the second region of the substrate.