US 12,405,305 B2
Reset for scan mode exit for devices with power-on reset generation circuitry
Shikhar Makkar, Faridabad (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Mar. 21, 2024, as Appl. No. 18/612,251.
Claims priority of provisional application 63/453,904, filed on Mar. 22, 2023.
Prior Publication US 2024/0319270 A1, Sep. 26, 2024
Int. Cl. G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31701 (2013.01); G01R 31/318544 (2013.01); G01R 31/318555 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a device core and scan flip flops associated with said device core;
a test access port (TAP) coupled to the scan flip flops, the TAP having a test clock (TCK) pin configured to receive a test clock (TCK) signal that clocks the TAP, a test data in (TDI) pin configured to receive a test data in (TDI) signal, and a test mode select (TMS) pin configured to receive a test mode select (TMS) signal;
a test control register (TCR) associated with the TAP;
wherein the TAP, in response to setting of the TCR to assert a scan mode signal, configures the scan flip flops for a scan testing and performs the scan testing on the device core;
wherein the TAP, in response to resetting of the TCR to deassert the scan mode signal, exits the scan testing; and
a reset circuit configured to reset the TCR in response to deassertion of both a scan enable (SE) signal applied to the TMS pin and a scan input (SI) signal applied to the TDI pin during a capture-phase of scan testing.