US 12,405,304 B2
Testing multi-cycle paths based on clock pattern
Nehal Patel, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 26, 2023, as Appl. No. 18/475,047.
Prior Publication US 2025/0102570 A1, Mar. 27, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/317 (2006.01); G01R 31/319 (2006.01)
CPC G01R 31/31727 (2013.01) [G01R 31/31723 (2013.01); G01R 31/31908 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network;
controlling a selector to set the enable configuration for the one or more multi-cycle paths; and
executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.