US 12,405,303 B2
Scan chain security circuit and driving method thereof
Sungho Kang, Seoul (KR); and Seokjun Jang, Paju-si (KR)
Assigned to UIF (University Industry Foundation), Yonsei University, Seoul (KR)
Filed by UIF (University Industry Foundation), Yonsei University, Seoul (KR)
Filed on Dec. 26, 2023, as Appl. No. 18/395,745.
Claims priority of application No. 10-2023-0023654 (KR), filed on Feb. 22, 2023.
Prior Publication US 2024/0280633 A1, Aug. 22, 2024
Int. Cl. G01R 31/317 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/31719 (2013.01) [G01R 31/318536 (2013.01); G01R 31/318572 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A scan chain security circuit comprising:
a scan chain including at least one flip-flop;
a scan path obfuscator configured to obfuscate a path of a pattern sequence input to at least one first flip-flop grouped at an input side of the scan chain, in response to a first control signal;
a scan path normalizer configured to normalize the path of the pattern sequence input to at least one second flip-flop grouped at an outside of the scan chain, in response to a second control signal;
at least one dummy flip-flop interposed between the at least one first flip-flop and the at least one second flip-flop to receive a test key included in the pattern sequence; and
a scan data obfuscator configured to damage and obfuscate an output pattern sequence output from the at least one second flip-flop, depending on whether a security key stored in a memory of a chip to be inspected is matched with the test key.