US 12,405,302 B2
Integrated circuit with off-state diagnosis for driver channels
Gaudenzia Bagnati, Pogliano Milanese (IT); Marzia Annovazzi, Buccinasco (IT); Diego Alagna, Milan (IT); and Lucia Maggio, Munich (DE)
Assigned to STMICROELECTRONICS S.R.L., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.R.L., Agrate Brianza (IT)
Filed on Feb. 23, 2022, as Appl. No. 17/678,763.
Prior Publication US 2023/0266381 A1, Aug. 24, 2023
Int. Cl. G01R 31/28 (2006.01); G01R 31/52 (2020.01); G01R 31/54 (2020.01); H03K 5/24 (2006.01); H03K 17/687 (2006.01); H03K 21/08 (2006.01)
CPC G01R 31/2851 (2013.01) [H03K 5/24 (2013.01); H03K 17/6874 (2013.01); H03K 21/08 (2013.01); G01R 31/52 (2020.01); G01R 31/54 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first driver channel including:
a first power transistor; and
a first output terminal;
a second driver channel including:
a second power transistor; and
a second output terminal; and
a driver control system including:
a first analog test circuit coupled to the first output terminal;
a second analog test circuit coupled to the second output terminal;
a first controller coupled to the first analog test circuit;
a second controller coupled to the second analog test circuit; and
a counter coupled to the first controller and the second controller, the counter configured to generate timing windows for off-state diagnosis for the first and second driver channels,
wherein the timing windows generated by the counter comprise at least a first off-state test phase and a second off-state test phase for each driver channel, and
wherein in the first off-state test phase, the respective analog test circuit detects whether a fault is present in the corresponding driver channel, and in the second off-state test phase, the respective analog test circuit identifies a type of fault when the fault is detected.