US 12,405,301 B2
Integrated current monitor
Miguel Rodriguez, Santa Clara, CA (US); Suhas Satheesh, Santa Clara, CA (US); Tezaswi Raja, Santa Clara, CA (US); and Nishit Harshad Shah, Santa Clara, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Apr. 20, 2023, as Appl. No. 18/303,829.
Prior Publication US 2024/0353475 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/28 (2006.01); H03K 17/687 (2006.01)
CPC G01R 31/2839 (2013.01) [G01R 31/2831 (2013.01); G01R 31/2837 (2013.01); G01R 31/2851 (2013.01); H03K 17/6872 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An integrated common current monitor (ICCM) for use with a semiconductor wafer, comprising:
DUT selection circuitry to select at least one of a plurality of DUTs; and
duty cycle measurement circuitry to determine electrical characteristics of the semiconductor wafer where the ICCM is located based on a current throughput of the selected at least one of the plurality of DUTs (IDUT).