US 12,404,597 B2
Electrochemical depositions of nanotwin copper materials
Jing Xu, Kalispell, MT (US); John L. Klocke, Kalispell, MT (US); Marvin L. Bernt, Kalispell, MT (US); Eric J. Bergman, Kalispell, MT (US); and Kwan Wook Roh, Kalispell, MT (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Apr. 20, 2023, as Appl. No. 18/304,200.
Application 18/304,200 is a division of application No. 17/411,305, filed on Aug. 25, 2021, granted, now 11,634,830.
Prior Publication US 2023/0272547 A1, Aug. 31, 2023
Int. Cl. C25D 3/38 (2006.01); C23C 14/18 (2006.01); C23C 16/455 (2006.01); C25D 5/00 (2006.01); C25D 5/02 (2006.01); C25D 5/54 (2006.01); C25D 7/12 (2006.01); H01L 21/28 (2006.01); H01L 21/288 (2006.01); H01L 21/768 (2006.01)
CPC C25D 3/38 (2013.01) [C23C 14/18 (2013.01); C23C 16/45525 (2013.01); C25D 5/02 (2013.01); C25D 5/54 (2013.01); C25D 5/617 (2020.08); C25D 7/123 (2013.01); H01L 21/28114 (2013.01); H01L 21/2885 (2013.01); H01L 21/76831 (2013.01); H01L 21/76873 (2013.01); H01L 21/76879 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit device structure comprising:
a patterned substrate comprising an opening, wherein the opening includes a bottom surface and one or more sidewall surfaces;
a seed layer coating the bottom surface and the one or more sidewall surfaces;
a barrier layer that covers the seed layer on the one or more sidewall surfaces while exposing the seed layer on the bottom surface; and
a metal-containing material filling the opening, wherein at least a top portion of the metal-containing material is characterized by a nanotwin crystal structure, and a bottom portion of the metal-containing material in contact with the bottom surface of the opening is characterized by a polycrystalline structure.