US 7,646,091 C1 (13,019th)
Semiconductor package and method using isolated VSS plane to accommodate high speed circuitry ground isolation
Maurice O. Othieno, Union City, CA (US); Chok J. Chia, Cupertino, CA (US); and Amar J. Amin, Milpitas, CA (US)
Filed by Maurice O. Othieno, Union City, CA (US); Chok J. Chia, Cupertino, CA (US); and Amar J. Amin, Milpitas, CA (US)
Assigned to BELL SEMICONDUCTOR, LLC
Reexamination Request No. 90/019,612, Aug. 6, 2024.
Reexamination Certificate for Patent 7,646,091, issued Jan. 12, 2010, Appl. No. 11/399,723, Apr. 6, 2006.
Ex Parte Reexamination Certificate issued on Aug. 27, 2025.
Int. Cl. H01L 23/50 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/50 (2013.01) [H01L 24/49 (2013.01); H01L 23/49838 (2013.01); H01L 24/48 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/4943 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/014 (2013.01); H01L 2924/10162 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01)]
OG exemplary drawing
AS A RESULT OF REEXAMINATION, IT HAS BEEN DETERMINED THAT:
The patentability of claims 1-14 is confirmed.
1. A semiconductor integrated circuit (IC) package which comprises:
a substrate having a first surface and a second surface
wherein;
a first layer of the substrate includes,
a first ground plane enabling electrical connection with low speed electronic circuitry, and
a second ground plane that is spatially separated and electrically isolated from the first ground plane, the second ground plane enabling electrical connection with high speed electronic circuitry;
a second layer of the substrate includes,
a third ground plane configured for electrical connection with low speed electronic circuitry, and
a fourth ground plane that is spatially separated and electrically isolated from the third ground plane, the third ground plane configured for electrical connection with high speed electronic circuitry;
a plurality of electrical connections that electrically connect the first ground plane with solder balls mounted on the second surface of the substrate;
a plurality of additional electrical connections that electrically connect the second ground plane with solder balls mounted on the second surface of the substrate; and
peripheral electrical contacts arranged on the substrate and configured for connection with electronic circuitry external to the package; and
at least one reference plane associated with each layer of the substrate and the ground planes included thereon.