US 12,075,713 B2
Phase-change memory and method of forming same
Jau-Yi Wu, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 23, 2023, as Appl. No. 18/321,843.
Application 17/666,230 is a division of application No. 16/727,363, filed on Dec. 26, 2019, granted, now 11,245,072, issued on Feb. 8, 2022.
Application 18/321,843 is a continuation of application No. 17/666,230, filed on Feb. 7, 2022, granted, now 11,696,519.
Prior Publication US 2023/0320239 A1, Oct. 5, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/826 (2023.02) [H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/231 (2023.02); H10N 70/841 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first dielectric layer;
a conductive line in the first dielectric layer;
a second dielectric layer over the conductive line and the first dielectric layer;
a bottom electrode within the second dielectric layer, the bottom electrode being electrically connected to the conductive line, the bottom electrode having a first width;
a first buffer layer over the bottom electrode, the first buffer layer having a second width;
a phase-change layer over the first buffer layer, the phase-change layer having a third width greater than the first width, the first buffer layer separating the phase-change layer from the bottom electrode;
a top electrode over the phase-change layer; and
a third dielectric layer over the second dielectric layer, the third dielectric layer extending along sidewalls of the phase-change layer.