| CPC H10N 50/80 (2023.02) [H01L 23/5226 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02)] | 20 Claims |
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1. A method for forming an integrated chip, the method comprising:
forming a memory element over a bottom electrode;
depositing a first dielectric layer over the memory element;
patterning the first dielectric layer to form a first opening in the first dielectric layer and directly over the memory element, wherein a distance between sidewalls of the first dielectric layer that define the first opening is less than a width of the memory element;
depositing a first conductive material in the first opening to form a top electrode in the first opening and directly over the memory element;
depositing a second dielectric layer over the top electrode and over the first dielectric layer;
patterning the second dielectric layer to form a second opening in the second dielectric layer and directly over the top electrode;
depositing a second conductive material in the second opening to form a first conductive line extending in a first direction and directly over the top electrode;
patterning the second dielectric layer to form a third opening in the second dielectric layer and adjacent to the first conductive line; and
depositing a third conductive material in the third opening to form a source line on a sidewall of the first conductive line and extending in a second direction transverse to the first direction, wherein the source line is electrically coupled to the top electrode.
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