| CPC H10K 59/131 (2023.02) [H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02); H10K 59/124 (2023.02)] | 16 Claims |
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1. A display substrate, wherein in a plane parallel to the display substrate, the display substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit at least comprises a storage capacitor, a driving transistor and at least one switching transistor; in a plane perpendicular to the display substrate, the display substrate comprises a semiconductor layer and a plurality of conductive layers; and
a gate electrode of the driving transistor and a gate electrode of the at least one switching transistor are arranged on different conductive layers respectively,
wherein the semiconductor layer is disposed on a base, the plurality of conductive layers comprises a first conductive layer, a second conductive layer and a third conductive layer disposed sequentially on one side of the semiconductor layer away from the base, the gate electrodes of the plurality of switching transistors are arranged on the first conductive layer, and the gate electrode of the driving transistor is arranged on the second conductive layer or the third conductive layer,
wherein the display substrate further comprises a second insulating layer, a third insulating layer and a fourth insulating layer; the second insulating layer covers the semiconductor layer, and the semiconductor layer comprises an active layer of the driving transistor and active layers of the plurality of switching transistors; the first conductive layer is disposed on the second insulating layer and comprises the gate electrodes of the plurality of switching transistors; the third insulating layer covers the first conductive layer, and the second conductive layer is disposed on the third insulating layer and comprises the gate electrode of the driving transistor; and the fourth insulating layer covers the second conductive layer, and the third conductive layer is disposed on the fourth insulating layer and comprises a first power line,
wherein the third conductive layer further comprises a first connecting electrode, a first via hole exposing the gate electrode of the driving transistor is provided in the fourth insulating layer, and a second via hole exposing the active layer of the switching transistor is provided in the second, third and fourth insulating layers; and the first connecting electrode is connected to the gate electrode of the driving transistor through the first via hole and is connected to the active layer of the switching transistor through the second via hole.
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