US 12,075,635 B2
Semiconductor device and method for manufacturing semiconductor device
Yasuhiko Takemura, Atsugi (JP); and Yoshiyuki Kurokawa, Sagamihara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jul. 9, 2021, as Appl. No. 17/371,517.
Application 17/371,517 is a continuation of application No. 16/898,573, filed on Jun. 11, 2020, granted, now 11,063,047.
Application 16/898,573 is a continuation of application No. 16/347,744, granted, now 10,692,869, issued on Jun. 23, 2020, previously published as PCT/IB2017/056970, filed on Nov. 8, 2017.
Claims priority of application No. 2016-224037 (JP), filed on Nov. 17, 2016.
Prior Publication US 2021/0335788 A1, Oct. 28, 2021
Int. Cl. H10B 99/00 (2023.01); G11C 11/401 (2006.01); G11C 11/405 (2006.01); G11C 11/409 (2006.01); G11C 11/4094 (2006.01); G11C 11/56 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01)
CPC H10B 99/00 (2023.02) [G11C 11/401 (2013.01); G11C 11/405 (2013.01); G11C 11/409 (2013.01); G11C 11/4094 (2013.01); G11C 11/565 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 27/127 (2013.01); H01L 28/60 (2013.01); H01L 29/423 (2013.01); H01L 29/49 (2013.01); H01L 29/66969 (2013.01); H01L 29/78642 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H10B 12/31 (2023.02); H01L 29/7833 (2013.01); H10B 12/0335 (2023.02); H10B 12/312 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor,
wherein:
a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
the one of the source and the drain of the second transistor is electrically connected to one electrode of the first capacitor,
the other electrode of the first capacitor is electrically connected to a first line,
a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
the one of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitor,
the other electrode of the second capacitor is electrically connected to a second line,
one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
an axis in a channel length direction of the first transistor corresponds to an axis in a channel length direction of the third transistor,
an axis in a channel length direction of the second transistor corresponds to an axis in a channel length direction of the fourth transistor,
a first semiconductor of the first transistor is silicon, and
a second semiconductor of the second transistor is a metal oxide comprising indium.