US 12,075,634 B2
RRAM memory cell with multiple filaments
Chin-Chieh Yang, New Taipei (TW); Chih-Yang Chang, Yuanlin Township (TW); Wen-Ting Chu, Kaohsiung (TW); and Yu-Wen Liao, New Taipei (TW)
Assigned to Taiwan SemiconductorManufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 6, 2023, as Appl. No. 18/347,794.
Application 16/202,576 is a division of application No. 15/904,963, filed on Feb. 26, 2018, granted, now 10,504,963, issued on Dec. 10, 2019.
Application 18/347,794 is a continuation of application No. 17/542,638, filed on Dec. 6, 2021, granted, now 11,737,290.
Application 17/542,638 is a continuation of application No. 16/587,693, filed on Sep. 30, 2019, granted, now 11,201,190, issued on Dec. 14, 2021.
Application 16/587,693 is a continuation of application No. 16/202,576, filed on Nov. 28, 2018, granted, now 10,680,038, issued on Jun. 9, 2020.
Claims priority of provisional application 62/552,078, filed on Aug. 30, 2017.
Prior Publication US 2023/0354618 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 63/00 (2023.01); G11C 13/00 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/10 (2006.01)
CPC H10B 63/82 (2023.02) [G11C 13/0011 (2013.01); G11C 13/0069 (2013.01); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/20 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); H10N 70/8836 (2023.02); G11C 13/0002 (2013.01); G11C 13/0023 (2013.01); G11C 13/004 (2013.01); G11C 2213/79 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/101 (2013.01); H10B 63/32 (2023.02); H10B 63/84 (2023.02); H10N 70/011 (2023.02); H10N 70/023 (2023.02); H10N 70/821 (2023.02); H10N 70/8845 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first resistive random access memory (RRAM) element and a second RRAM element over a substrate;
a conductive element arranged below the first RRAM element and the second RRAM element, wherein the conductive element electrically couples the first RRAM element to the second RRAM element;
an upper insulating layer continuously extending over the first RRAM element and the second RRAM element; and
an upper inter-level dielectric (ILD) structure laterally surrounding the first RRAM element and the second RRAM element, wherein the upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.