CPC H10B 63/82 (2023.02) [G11C 13/0011 (2013.01); G11C 13/0069 (2013.01); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/20 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); H10N 70/8836 (2023.02); G11C 13/0002 (2013.01); G11C 13/0023 (2013.01); G11C 13/004 (2013.01); G11C 2213/79 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/101 (2013.01); H10B 63/32 (2023.02); H10B 63/84 (2023.02); H10N 70/011 (2023.02); H10N 70/023 (2023.02); H10N 70/821 (2023.02); H10N 70/8845 (2023.02)] | 20 Claims |
1. An integrated chip, comprising:
a first resistive random access memory (RRAM) element and a second RRAM element over a substrate;
a conductive element arranged below the first RRAM element and the second RRAM element, wherein the conductive element electrically couples the first RRAM element to the second RRAM element;
an upper insulating layer continuously extending over the first RRAM element and the second RRAM element; and
an upper inter-level dielectric (ILD) structure laterally surrounding the first RRAM element and the second RRAM element, wherein the upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.
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