US 12,075,633 B2
Vertical metal oxide semiconductor channel selector transistor and methods of forming the same
Yong-Jie Wu, Tainan (TW); Yen-Chung Ho, Hsinchu (TW); Mauricio Manfrini, Hsinchu (TW); Chung-Te Lin, Taiwan (TW); and Pin-Cheng Hsu, Pin-Cheng Hsu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on May 16, 2023, as Appl. No. 18/317,958.
Application 17/843,118 is a division of application No. 16/909,109, filed on Jun. 23, 2020, granted, now 11,374,057, issued on Jun. 28, 2022.
Application 18/317,958 is a continuation of application No. 17/843,118, filed on Jun. 17, 2022, granted, now 11,696,453.
Prior Publication US 2023/0284461 A1, Sep. 7, 2023
Int. Cl. H10B 63/00 (2023.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 53/30 (2023.01); H10B 53/40 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/34 (2023.02) [H01L 29/66969 (2013.01); H01L 29/78642 (2013.01); H01L 29/7869 (2013.01); H10B 53/30 (2023.02); H10B 53/40 (2023.02); H10B 63/80 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10N 70/24 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device structure comprising at least one selector device, wherein each of the at least one selector device comprises:
a vertical stack including a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate;
a gate dielectric layer contacting a sidewall of the bottom electrode;
a gate electrode laterally surrounded by the gate dielectric layer;
a via-level dielectric layer underlying the gate dielectric layer and laterally surrounding a via portion of the bottom electrode; and
dielectric isolation structure contacting an additional sidewall of the bottom electrode and contacting a sidewall of the top electrode.