US 12,075,632 B2
Electronic device with variable resistance layers and insulating layers alternately stacked and method of manufacturing the same class
Si Jung Yoo, Seoul (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on May 15, 2023, as Appl. No. 18/317,680.
Application 18/317,680 is a continuation of application No. 17/751,417, filed on May 23, 2022, abandoned.
Application 17/751,417 is a continuation of application No. 16/903,908, filed on Jun. 17, 2020, granted, now 11,362,139, issued on Jun. 14, 2022.
Claims priority of application No. 10-2019-0175654 (KR), filed on Dec. 26, 2019.
Prior Publication US 2023/0284459 A1, Sep. 7, 2023
Int. Cl. H10B 63/00 (2023.01); G11C 5/02 (2006.01); G11C 13/00 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/00 (2023.02) [G11C 5/025 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/8828 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A semiconductor memory comprising:
first variable resistance layers and insulating layers alternately stacked;
conductive pillars passing through the first variable resistance layers and the insulating layers;
a slit insulating layer vertically passing through the insulating layers, extending in a first direction, and being disposed in a second direction of the insulating layers, the second direction intersecting with the first direction;
conductive layers disposed between the slit insulating layer and the first variable resistance layers; and
electrode layers disposed between the conductive layers and the first variable resistance layers, each of the electrode layers being in contact with the slit insulating layer,
wherein the first variable resistance layers remain in an amorphous state during a program operation.