US 12,075,626 B2
Memory window of MFM MOSFET for small cell size
Hai-Dang Trinh, Hsinchu (TW); Yi Yang Wei, Hsinchu (TW); Bi-Shen Lee, Hsinchu (TW); Fa-Shen Jiang, Taoyuan (TW); Hsun-Chung Kuang, Hsinchu (TW); and Cheng-Yuan Tsai, Chu-Pei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 9, 2023, as Appl. No. 18/332,080.
Application 18/332,080 is a division of application No. 17/346,627, filed on Jun. 14, 2021, granted, now 11,723,212.
Claims priority of provisional application 63/166,413, filed on Mar. 26, 2021.
Prior Publication US 2023/0320103 A1, Oct. 5, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 49/02 (2006.01); H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) [H01L 28/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first interconnect dielectric layers over a substrate and surrounding a first wire;
a second interconnect dielectric layer over the first interconnect dielectric layer and surrounding a first via;
a bottom electrode disposed over a conductive structure and extending through the first interconnect dielectric layer and the second interconnect dielectric layer;
a top electrode disposed over the bottom electrode; and
a ferroelectric layer disposed between and contacting the bottom electrode and the top electrode, wherein the ferroelectric layer comprises a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion, wherein the first lower horizontal portion is below an entirety of the second interconnect dielectric layer, and wherein the first upper horizontal portion is above the entirety of the second interconnect dielectric layer.