US 12,075,623 B2
Method of forming a stacked memory structure with insulating patterns
Changhan Kim, Icheon-si (KR); In Ku Kang, Icheon-si (KR); and Sun Young Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 17, 2023, as Appl. No. 18/186,062.
Application 18/186,062 is a continuation of application No. 16/992,926, filed on Aug. 13, 2020, granted, now 11,637,124.
Claims priority of application No. 10-2020-0021284 (KR), filed on Feb. 20, 2020.
Prior Publication US 2023/0232631 A1, Jul. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42324 (2013.01); H01L 29/4234 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02); H10B 63/845 (2023.02); H10N 70/066 (2023.02); H10N 70/231 (2023.02)] 6 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a stacked structure with first material layers and second material layers that are alternately stacked on each other;
forming a hard mask pattern on the stacked structure;
forming a first opening that penetrates the stacked structure;
forming insulating patterns on respective second material layers, wherein the insulating patterns protrude farther into the first opening than a sidewall of the hard mask pattern;
forming a memory layer that fills a space between the insulating patterns, in the first opening; and
forming a channel structure in the memory layer.