US 12,075,618 B2
Input and digital output mechanisms for analog neural memory in a deep learning artificial neural network
Hieu Van Tran, San Jose, CA (US); Thuan Vu, San Jose, CA (US); Stephen Trinh, San Jose, CA (US); Stanley Hong, San Jose, CA (US); Toan Le, Ho Chi Minh (VN); Nghia Le, Ho Chi Minh (VN); and Hien Pham, Ho Chi Minh (VN)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/133,395.
Application 17/133,395 is a continuation in part of application No. 16/919,697, filed on Jul. 2, 2020, granted, now 11,482,530.
Application 16/919,697 is a continuation of application No. 16/231,231, filed on Dec. 21, 2018, granted, now 10,741,568.
Claims priority of provisional application 62/746,470, filed on Oct. 16, 2018.
Prior Publication US 2021/0118894 A1, Apr. 22, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/42 (2023.01); G06N 3/08 (2023.01); G11C 16/04 (2006.01); H01L 29/788 (2006.01)
CPC H10B 41/42 (2023.02) [G06N 3/08 (2013.01); G11C 16/0425 (2013.01); H01L 29/7883 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method comprising:
providing a plurality of input bits to an input circuit sequentially to an array of non-volatile memory cells;
for each of the plurality of input bits:
generating, by the input circuit, an input signal in response to the input bit;
applying the input signal to a terminal of a selected non-volatile memory cell in the array;
receiving, by an output circuit from the array, an output generated in response to the input bit;
converting the output into a digital output; and
shifting the digital output based on the bit location of the input bit within the plurality of input bits to generate a shifted result; and
adding the shifted results for all of the plurality of input bits to yield a digital output.
 
9. A method comprising:
providing a plurality of input bits to an input circuit sequentially to an array of non-volatile memory cells; and
for each of the plurality of input bits:
generating, by the input circuit, an input signal in response to the input bit, wherein the input signal comprises an analog bias level component and a pulsewidth component;
applying the input signal to a terminal of a selected non-volatile memory cell in the array;
receiving, by an output circuit, an output generated in response to the input bit; and
converting the output into a digital output.
 
15. A method comprising:
providing a plurality of input bits to an input circuit sequentially to an array of non-volatile memory cells; and
for each of the plurality of input bits:
generating, by the input circuit, an input signal in response to the multi-bits of the input bits, wherein the input signal is an analog bias level;
applying the input signal to a terminal of a selected non-volatile memory cell in the array; and
receiving, by an output circuit, an output generated in response to the input bit.