CPC H10B 41/42 (2023.02) [G06N 3/08 (2013.01); G11C 16/0425 (2013.01); H01L 29/7883 (2013.01)] | 22 Claims |
1. A method comprising:
providing a plurality of input bits to an input circuit sequentially to an array of non-volatile memory cells;
for each of the plurality of input bits:
generating, by the input circuit, an input signal in response to the input bit;
applying the input signal to a terminal of a selected non-volatile memory cell in the array;
receiving, by an output circuit from the array, an output generated in response to the input bit;
converting the output into a digital output; and
shifting the digital output based on the bit location of the input bit within the plurality of input bits to generate a shifted result; and
adding the shifted results for all of the plurality of input bits to yield a digital output.
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9. A method comprising:
providing a plurality of input bits to an input circuit sequentially to an array of non-volatile memory cells; and
for each of the plurality of input bits:
generating, by the input circuit, an input signal in response to the input bit, wherein the input signal comprises an analog bias level component and a pulsewidth component;
applying the input signal to a terminal of a selected non-volatile memory cell in the array;
receiving, by an output circuit, an output generated in response to the input bit; and
converting the output into a digital output.
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15. A method comprising:
providing a plurality of input bits to an input circuit sequentially to an array of non-volatile memory cells; and
for each of the plurality of input bits:
generating, by the input circuit, an input signal in response to the multi-bits of the input bits, wherein the input signal is an analog bias level;
applying the input signal to a terminal of a selected non-volatile memory cell in the array; and
receiving, by an output circuit, an output generated in response to the input bit.
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