US 12,075,615 B2
Semiconductor device
Jaehun Jung, Seongnam-si (KR); Suhwan Lim, Hanam-si (KR); and Hyeyoung Kwon, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 18, 2021, as Appl. No. 17/205,563.
Claims priority of application No. 10-2020-0075576 (KR), filed on Jun. 22, 2020.
Prior Publication US 2021/0398998 A1, Dec. 23, 2021
Int. Cl. H01L 27/11556 (2017.01); G11C 5/06 (2006.01); H01L 23/538 (2006.01); H01L 27/11582 (2017.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 5/06 (2013.01); H01L 23/5386 (2013.01); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a stack structure comprising interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular to an upper surface of the substrate;
a channel structure that penetrates the stack structure;
a contact plug on the channel structure; and
a bit line on the contact plug,
wherein the channel structure comprises a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure, and
wherein the pad structure comprises a pad pattern, a first pad layer, and a second pad layer,
wherein the first pad layer is between the channel layer and the pad pattern,
wherein the second pad layer comprises a first portion that is between the channel layer and the first pad layer, and a second portion that is between the first pad layer and the core pattern,
wherein the second portion of the second pad layer directly contacts a side surface of the pad pattern, and
wherein a side surface of the first pad layer directly contacts the side surface of the pad pattern.