US 12,075,614 B2
MIM memory cell with backside interconnect structures
Meng-Sheng Chang, Chu-bei (TW); Chia-En Huang, Xinfeng Township (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu (TW)
Filed on Sep. 13, 2021, as Appl. No. 17/473,678.
Claims priority of provisional application 63/188,164, filed on May 13, 2021.
Prior Publication US 2022/0367489 A1, Nov. 17, 2022
Int. Cl. H10B 20/20 (2023.01); H01L 23/525 (2006.01); H10B 20/25 (2023.01)
CPC H10B 20/20 (2023.02) [H01L 23/5256 (2013.01); H10B 20/25 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate having a first side and a second side that is opposite to the first side;
a transistor disposed on the first side of the substrate; and
a capacitor electrically connected to the transistor and including a first terminal, a second terminal, and an insulation layer interposed between the first and second terminals, at least the insulation layer disposed on the second side of the substrate;
wherein the first terminal includes an interconnect structure disposed directly over the insulation layer on the second side, wherein the insulation layer has a width less than a width of a bottom surface of the interconnect structure, and wherein the transistor and the capacitor form a one-time programmable (OTP) memory cell.