US 12,075,608 B2
Multi-gate semiconductor device for memory and method for forming the same
Huai-Ying Huang, Taipei County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 16, 2021, as Appl. No. 17/377,790.
Prior Publication US 2023/0015575 A1, Jan. 19, 2023
Int. Cl. H10B 10/00 (2023.01); G11C 11/412 (2006.01)
CPC H10B 10/125 (2023.02) [G11C 11/412 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first static random access memory (SRAM) cell comprising:
a first pull-up transistor and a second pull-up transistor;
a first pull-down transistor and a second pull-down transistor; and
a first pass-gate transistor and a second pass-gate transistor;
a second SRAM cell comprising:
a third pull-up transistor and a fourth pull-up transistor;
a third pull-down transistor and a fourth pull-down transistor; and
a third pass-gate transistor and a fourth pass-gate transistor;
a first inter transistor and a second inter transistor electrically connected to the first SRAM cell and the second SRAM cell;
a first bit line coupled to the first pass-gate transistor of the first SRAM cell;
a second bit line coupled to the fourth pass-gate transistor of the second SRAM cell; and
a third bit line coupled to the second pass-gate transistor of the first SRAM and the third pass-gate transistor of the second SRAM,
wherein a source/drain of the first inter transistor is electrically connected to a source/drain of the second pull-up transistor of the first SRAM cell and a source/drain of the second pass-gate transistor of the first SRAM cell, and a source/drain of the second inter transistor is electrically connected to a source/drain of the third pull-up transistor of the second SRAM cell and a source/drain of the third pass-gate transistor of the second SRAM cell.