US 12,075,607 B2
Semiconductor device
Yi-Jing Lee, Hsinchu (TW); Tsz-Mei Kwok, Hsinchu (TW); Ming-Hua Yu, Hsinchu (TW); and Kun-Mu Li, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Dec. 21, 2022, as Appl. No. 18/069,765.
Application 15/702,569 is a division of application No. 14/938,311, filed on Nov. 11, 2015, granted, now 9,768,178, issued on Sep. 19, 2017.
Application 18/069,765 is a continuation of application No. 17/089,580, filed on Nov. 4, 2020, granted, now 11,574,916.
Application 17/089,580 is a continuation of application No. 16/927,751, filed on Jul. 13, 2020, granted, now 11,355,500, issued on Jun. 7, 2022.
Application 16/927,751 is a continuation of application No. 16/234,283, filed on Dec. 27, 2018, granted, now 10,714,487, issued on Jul. 14, 2020.
Application 16/234,283 is a continuation of application No. 15/702,569, filed on Sep. 12, 2017, granted, now 10,170,483, issued on Jan. 1, 2019.
Prior Publication US 2023/0124966 A1, Apr. 20, 2023
Int. Cl. H10B 10/00 (2023.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01)
CPC H10B 10/12 (2023.02) [H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/7848 (2013.01); H01L 29/7853 (2013.01); H01L 29/165 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor substrate;
a semiconductor fin over the semiconductor substrate, wherein the semiconductor fin comprises a channel portion and recessed portions on opposite sides of the channel portion;
a gate structure over the channel portion of the semiconductor fin;
a first source/drain epitaxy structure and a second source/drain epitaxy structure over the recessed portions of the semiconductor fin, respectively;
a first dielectric fin sidewall structure and a second dielectric fin sidewall structure on opposite sides of the first source/drain epitaxy structure, wherein a portion of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure; and
an isolation structure surrounding the semiconductor fin, wherein a height of the first dielectric fin sidewall structure and a height of a portion of the channel portion of the semiconductor fin over the isolation structure satisfy a condition: 0.1≤(H1/H2)≤0.5, wherein H1 is the height of the first dielectric fin sidewall structure and H2 is the height of the portion of the channel portion of the semiconductor fin over the isolation structure.