CPC H05K 1/025 (2013.01) [H01P 3/08 (2013.01); H01L 25/18 (2013.01); H05K 1/117 (2013.01); H05K 1/18 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/09245 (2013.01); H05K 2201/09336 (2013.01); H05K 2201/09672 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10545 (2013.01)] | 20 Claims |
1. A printed circuit board, comprising:
a first reference plane configured to distribute a first voltage applied thereto across a surface area of the first reference plane;
a second reference plane extending parallel to the first reference plane, and configured to distribute a second voltage applied thereto across a surface area of the second reference plane;
a first layer, which extends between the first reference plane and the second reference plane, and includes one or more first signal lines extending adjacent the first reference plane, said first layer is divided into: (i) a first region in which the one or more first signal lines are disposed, (ii) a second region containing an additional plane that is configured to receive a third voltage and has smaller surface area relative to the surface areas of the first and second reference planes, and (iii) a third region containing a dielectric layer; and
a second layer, which extends between the first reference plane and the second reference plane, and includes one or more second signal lines extending adjacent the second reference plane, said second signal lines having linewidths that vary as a function of whether they are vertically aligned with the first region, the second region, or the third region.
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