CPC H04W 74/08 (2013.01) [H04L 45/24 (2013.01); H04L 47/12 (2013.01)] | 19 Claims |
1. A device for data transmission, comprising:
at least one processor; and
a memory, configured to store processor-executable instructions,
wherein when executing the processor-executable instructions, the at least one processor is configured to:
determine, from a plurality of links, available links that support certain data and certain category types of data to be transmitted to second devices, wherein each of the second devices supports one or more available links;
add the data to a transmission queue of each of the available links corresponding to the data;
determine a result of transmission right contention of the available links based on a transmission priority order of certain category types of data supported by the available links for transmitting the data;
transmit the data based on the result of transmission right contention of the available links; and
in response to the data that has been transmitted over one or more of the available links being still in the transmission queues of other available links, delete the data from the transmission queues of the other available links,
wherein the at least one processor is further configured to:
in response to transmission rights being acquired by data of different categories to be sent to different second devices in two or more of the available links at the same time, transmit the data over the two or more available links to the different second devices, and delete the data from transmission queues of other available links; and/or
in response to transmission rights being acquired by different data of a same category to be sent to different second devices in two or more of the available links at the same time, transmit the data over the two or more available links to the different second devices, and delete the data from transmission queues of other available links.
|