CPC H04W 72/53 (2023.01) [H04W 24/08 (2013.01); H04W 72/0453 (2013.01); H04W 72/23 (2023.01)] | 9 Claims |
7. A terminal, comprising a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, wherein when executing the computer program, the processor implements a following step:
receiving a physical downlink control channel PDCCH in a search space associated with a CORESET, wherein the CORESET comprises at least two search spaces, and the at least two search spaces in the CORESET occupy different locations in frequency domain;
frequency domain resources occupied by the at least two search spaces are distributed in different channel monitoring subbands, wherein initial frequency domain offsets of the at least two search spaces are the same or different; and
frequency domain offset amplitudes of the at least two search spaces in the CORESET corresponding to different time units are the same or different.
|