CPC H04N 5/04 (2013.01) [H04N 5/772 (2013.01); H04N 23/617 (2023.01); H04N 23/665 (2023.01); H04N 23/80 (2023.01)] | 18 Claims |
1. An imaging element comprising:
a reception interface that receives an imaging synchronization signal related to a timing of imaging, and at least one output synchronization signal related to a timing of output of image data obtained by imaging, from an exterior of the imaging element;
a memory that stores the image data obtained by imaging at a first frame rate in accordance with the imaging synchronization signal received by the reception interface; and
an output circuit that outputs the image data stored in the memory at a second frame rate in accordance with the output synchronization signal received by the reception interface, wherein:
the first frame rate is greater than or equal to the second frame rate,
the reception interface includes a first reception interface and a second reception interface,
the reception interface is incorporated in the imaging element,
the first reception interface receives the imaging synchronization signal from the exterior, and
the second reception interface receives the output synchronization signal from the exterior.
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