US 12,075,179 B2
Image signal and phase detection autofocus signal extraction and storage in an arithmetic logic unit
Rui Wang, San Jose, CA (US)
Assigned to OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on Oct. 18, 2022, as Appl. No. 18/047,588.
Prior Publication US 2024/0129650 A1, Apr. 18, 2024
Int. Cl. H04N 25/772 (2023.01); G06F 7/501 (2006.01); G06F 7/57 (2006.01)
CPC H04N 25/772 (2023.01) [G06F 7/501 (2013.01); G06F 7/57 (2013.01)] 51 Claims
OG exemplary drawing
 
1. An arithmetic logic unit (ALU), comprising:
a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs of the GC generator in response to a comparator output;
a signal latch stage coupled to latch outputs of the front end latch stage in response to a signal latch enable signal;
a GC to binary stage coupled to generate a binary representation of the GC outputs latched in the signal latch stage;
an adder stage including first inputs and second inputs, wherein the first inputs of the adder stage are coupled to receive outputs of the GC to binary stage, wherein outputs of the adder stage are generated in response to the first inputs and the second inputs of the adder stage;
an adder input latch stage coupled to latch outputs of the GC to binary stage, wherein the adder input latch stage comprises:
first adder input latches configured to latch the outputs of the GC to binary stage in response to a first adder input latch enable signal; and
second adder input latches configured to latch the outputs of the GC to binary stage in response to a second adder input latch enable signal; and
an adder input multiplexer stage, wherein first inputs of the adder input multiplexer stage are coupled to receive outputs of the first adder input latches, wherein second inputs of the adder input multiplexer stage are coupled to receive outputs of the second adder input latches, wherein the second inputs of the adder stage are coupled to receive outputs of the adder input multiplexer stage.