US 12,075,074 B2
Systems and methods for multi-core image encoding
Liviu R Morogan, San Jose, CA (US); Athanasios Leontaris, Cupertino, CA (US); Mark P Rygh, Union City, CA (US); and Sorin C Cismas, Saratoga, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 18, 2022, as Appl. No. 17/675,414.
Claims priority of provisional application 63/248,253, filed on Sep. 24, 2021.
Prior Publication US 2023/0102584 A1, Mar. 30, 2023
Int. Cl. H04N 19/436 (2014.01); H04N 19/127 (2014.01); H04N 19/157 (2014.01); H04N 19/169 (2014.01); H04N 19/172 (2014.01); H04N 19/186 (2014.01); H04N 19/40 (2014.01); H04N 19/423 (2014.01)
CPC H04N 19/436 (2014.11) [H04N 19/127 (2014.11); H04N 19/157 (2014.11); H04N 19/172 (2014.11); H04N 19/186 (2014.11); H04N 19/1883 (2014.11); H04N 19/40 (2014.11); H04N 19/423 (2014.11)] 20 Claims
OG exemplary drawing
 
1. An electronic device comprising:
video encoder circuitry that processes received video data, wherein the video encoder circuitry comprises:
a plurality of processing cores that process the received video data; and
a controller, wherein the controller is configured to:
direct a first processing core of the plurality of processing cores to process a first quad-row of the received video data and send first neighbor data associated with the first quad-row of the received video data directly to a second processing core of the plurality of processing cores via a wired connection connecting a first direct memory access of the first processing core of the plurality of processing cores to a second direct memory access of the second processing core of the plurality of processing cores while the first quad-row is being processed by the first processing core of the plurality of processing cores, wherein the second processing core of the plurality of processing cores is configured to process a second quad-row using the first neighbor data.