CPC H04N 19/117 (2014.11) [H04N 19/132 (2014.11); H04N 19/188 (2014.11); H04N 19/82 (2014.11)] | 12 Claims |
1. A decoder comprising:
circuitry; and
memory coupled to the circuitry,
wherein, in operation, the circuitry:
derives a parameter from information included in a header of a bitstream;
generates a second image by applying a filtering process to reconstructed samples in a first image, the filtering process including applying an adaptive loop filtering process to the reconstructed samples in the first image;
determines whether the parameter has a predefined value;
generates an inter prediction image using one of the first image and the second image, the first image being used to generate the inter prediction image when the parameter does not have the predefined value, and the second image being used to generate the inter prediction image when the parameter has the predefined value;
decodes a third image by adding a difference image and the inter prediction image; and
after decoding the third image by adding the difference image and the inter-prediction image generated by using the one of the first image and the second image, outputs the second image generated by applying the filtering process to the reconstructed samples in the first image, the second image being output after decoding the third image regardless of whether inter-prediction image is generated using the first image or the second image.
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