US 12,074,992 B2
Method and apparatus for logic cell-based PUF generators
Shih-Lien Linus Lu, Hsinchu (TW); and Cormac Michael O'Connell, Kanata (CA)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/232,336.
Application 18/232,336 is a continuation of application No. 17/107,816, filed on Nov. 30, 2020, granted, now 11,811,953.
Application 17/107,816 is a continuation of application No. 16/138,690, filed on Sep. 21, 2018, granted, now 10,880,102.
Claims priority of provisional application 62/642,921, filed on Mar. 14, 2018.
Prior Publication US 2023/0388135 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/32 (2006.01)
CPC H04L 9/3278 (2013.01) [H04L 9/3247 (2013.01); H04L 2209/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A physical unclonable function (PUF) generator comprising:
a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row; and
a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to allow each of the plurality of bit cells to have a first metastable logical state; stabilize the first metastable logical state of each of the plurality of bit cells to a second logical state; determine the second logical state of each of the plurality of bit cells; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature,
wherein each of the plurality of bit cells comprises at least one enable transistor, at least one access transistor, and at least one storage node.