US 12,074,818 B2
TCI chain design
Jie Cui, San Jose, CA (US); Yang Tang, San Jose, CA (US); Qiming Li, Beijing (CN); Dawei Zhang, Saratoga, CA (US); Haitong Sun, Cupertino, CA (US); Hong He, San Jose, CA (US); Huaning Niu, San Jose, CA (US); Manasa Raghavan, Sunnyvale, CA (US); Xiang Chen, Campbell, CA (US); and Yushu Zhang, Beijing (CN)
Assigned to Apple Inc., Cupertino, CA (US)
Appl. No. 17/593,280
Filed by Apple Inc., Cupertino, CA (US)
PCT Filed Jan. 13, 2021, PCT No. PCT/CN2021/071583
§ 371(c)(1), (2) Date Sep. 14, 2021,
PCT Pub. No. WO2022/151090, PCT Pub. Date Jul. 21, 2022.
Prior Publication US 2023/0171054 A1, Jun. 1, 2023
Int. Cl. H04W 72/21 (2023.01); H04L 5/00 (2006.01)
CPC H04L 5/0048 (2013.01) [H04L 5/001 (2013.01); H04W 72/21 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A processor of a user equipment (UE) configured to perform operations comprising:
receiving TCI state configurations for a plurality of signals, wherein a first state configuration comprises a first port for a first signal being quasi-co-located (QCL) to a second port of a second signal and a second state configuration comprises the second port of the second signal being QCL to a third port of a third signal; and
determining a TCI chain comprising the first, second and third signals so that channel measurements for each one of the first, second and third signals are applied to channel measurements for each other one of the first, second and third signals,
wherein at least one of the first, second or third signals is an uplink (UL) signal.