CPC H04L 49/9094 (2013.01) [H04L 47/24 (2013.01); H04L 65/65 (2022.05)] | 20 Claims |
1. A server comprising:
processing circuitry and memory hardware, the memory hardware comprising:
a first buffer configured to store packets from a first device;
a decoder configured to decode the packets to obtain decoded packets;
an encoder configured to:
encode the decoded packets to obtain encoded packets, and
transmit the encoded packets to a storage unit configured to allow data access when a data packet processing speed is below a threshold processing speed; and
a second buffer configured to:
fetch the encoded packets from the storage unit, and
cause a transmitter to transmit the encoded packets to a second device.
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