US 12,074,800 B2
Memory control system and memory control method
Chi-Shao Lai, Hsinchu (TW); and Hsu-Tung Shih, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on May 12, 2023, as Appl. No. 18/196,620.
Claims priority of application No. 111120515 (TW), filed on Jun. 1, 2022.
Prior Publication US 2023/0396552 A1, Dec. 7, 2023
Int. Cl. H04L 47/24 (2022.01); H04L 41/16 (2022.01); H04L 47/56 (2022.01)
CPC H04L 47/24 (2013.01) [H04L 41/16 (2013.01); H04L 47/56 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory control system, comprising:
a front-end circuitry configured to receive a plurality of access requests from a plurality of devices, and adjust an order of the plurality of devices to access a memory according to a plurality of control signals;
a traffic scheduling circuitry configured to generate a plurality of traffic data based on the plurality of access requests and analyze the plurality of traffic data based on a neural network model and a predetermined rule, in order to determine the plurality of control signals; and
a back-end circuitry configured to adjust a task schedule of the memory according to the plurality of control signals,
wherein the front-end circuitry is coupled to a first device in the plurality of devices via a first connection port in a plurality of connection ports to receive a plurality of first access requests in the plurality of access requests, and the traffic scheduling circuitry is configured to:
store a delay time of a corresponding one of the plurality of first access requests and a number of outstanding requests in the plurality of first access requests when the first device receives a response to the corresponding one of the plurality of first access requests, and
generate first data in the plurality of traffic data that corresponds to the first connection port based on the delay time and the number of outstanding requests in the plurality of first access requests.