CPC H04L 41/0668 (2013.01) [H04L 41/0645 (2013.01); H04L 41/065 (2013.01); H04L 41/12 (2013.01); H04L 43/0835 (2013.01); H04L 43/0858 (2013.01); H04L 43/103 (2013.01); H04L 45/22 (2013.01)] | 27 Claims |
1. A computing device comprising:
a memory;
an interface; and
one or more processors in communication with the memory and the interface, the one or more processors operative to:
generate a first network topology comprising a plurality of network paths,
measure performance information across each of the plurality of network paths in an ordered manner;
aggregate performance information across individual paths of the plurality of network paths, wherein aggregating performance information across individual paths comprises aggregating performance information across individual nodes and individual links of the individual paths; and
determine one or more root causes for detected failures on individual paths of the plurality of network paths based on processing the aggregated performance information corresponding to the individual nodes and individual links of the individual paths.
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