US 12,074,738 B2
Semiconductor device
Jahoon Jin, Hwaseong-si (KR); Kyunghwan Min, Hwaseong-si (KR); Soomin Lee, Hwaseong-si (KR); Sang-Ho Kim, Suwon-si (KR); Jihoon Lim, Suwon-si (KR); Sodam Ju, Hwaseong-si (KR); and Hyun Su Chea, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 23, 2022, as Appl. No. 17/951,482.
Claims priority of application No. 10-2021-0165139 (KR), filed on Nov. 26, 2021; and application No. 10-2022-0027922 (KR), filed on Mar. 4, 2022.
Prior Publication US 2023/0171134 A1, Jun. 1, 2023
Int. Cl. H04L 25/03 (2006.01); H04B 1/16 (2006.01); H04L 1/20 (2006.01); H04L 7/00 (2006.01)
CPC H04L 25/03878 (2013.01) [H04B 1/16 (2013.01); H04L 1/205 (2013.01); H04L 7/0079 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n−1 first signals having two signal levels; and
a jitter compensation circuit configured to receive the n−1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n−1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n−1 first signals transitions from the second signal level to the first signal level, to output n−1 second signals.