US 12,074,737 B2
SerDes receiver with optimized CDR pulse shaping
Chaitanya Palusa, San Jose, CA (US); Rob Abbott, Kanata (CA); Rolando Ramirez, Hsinchu (TW); Wei-Li Chen, Hsinchu (TW); Dirk Pfaff, Ontario (CA); Cheng-Hsiang Hsieh, Taipei (TW); and Fan-ming Kuo, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 31, 2022, as Appl. No. 17/589,314.
Application 17/589,314 is a continuation of application No. 17/157,114, filed on Jan. 25, 2021, granted, now 11,240,075.
Application 17/157,114 is a continuation of application No. 16/741,188, filed on Jan. 13, 2020, granted, now 10,904,044, issued on Jan. 26, 2021.
Claims priority of provisional application 62/799,316, filed on Jan. 31, 2019.
Prior Publication US 2022/0158878 A1, May 19, 2022
Int. Cl. H04L 25/03 (2006.01); H03K 5/00 (2006.01); H03K 5/135 (2006.01); H04L 25/02 (2006.01); H04L 27/01 (2006.01)
CPC H04L 25/03878 (2013.01) [H03K 5/135 (2013.01); H04L 25/028 (2013.01); H04L 25/03038 (2013.01); H04L 25/03057 (2013.01); H04L 27/01 (2013.01); H03K 2005/00052 (2013.01); H03K 2005/00065 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock data recovery method comprising:
receiving a first input signal from an analog to digital controller;
equalizing the first input signal based on a plurality of tap coefficients to generate a first output signal;
generating an equalized output signal by a decision feedforward equalizer based on the first output signal and a feedback signal;
generating an error signal based on the equalized output signal from the decision feedforward equalizer; and
providing an adjustment signal to the analog to digital controller based on the first output signal, wherein the first output signal is tapped, with a clock data recovery adaptation, at an intermediate node of an equalization data path at which signal is not fully equalized to generate the adjustment signal.